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CXA3572R
Driver/Timing Generator for Color LCD Panels
Description The CXA3572R is an IC designed to drive the color LCD panel ACX306. This IC greatly reduces the number of peripheral circuits and parts by incorporating a RGB driver and timing generator for video signals and a VCO onto a single chip. This chip has a built-in serial interface circuit and electronic attenuators which allow various settings to be performed by microcomputer control, etc. Features * Color LCD panel ACX306 driver * Supports NTSC and PAL systems * Supports Y/color difference and RGB inputs * Supports OSD input * Power saving function (clock stopped) * Various setting control using a serial interface circuit (asynchronous type) * Electronic attenuators (D/A converter) * VCO (no external oscillator circuit) * LPF (fc variable) * COMMON and PSIG output circuits * Sharpness function * 2-point correction circuit * R, G, B signal delay time adjustment circuit * Sync separation circuit * D/A output pin (0 to 3V, 8 level output) * Output polarity inversion circuit * Supports AC drive for LCD panel during no signal Applications Compact LCD monitors, etc. 48 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25C) * Supply voltage VCC1 5.5 V VCC2 15 V VDD 4.6 V * Analog input pin voltage VINA1 (Pins 18, 19, 20, 22, 23, 24 and 25) GND - 0.3 to VCC1 + 0.3 V VINA2 (Pin 16) GND - 0.3 to VCC2 + 0.3 V * Digital input pin voltage VIND (Pins 34 and 35) VSS - 0.3 to +5.5 V * Common input pin voltage VINAD (Pins 31, 32 and 33) GND, VSS - 0.3 to +5.5 V * Operating temperature Topr -15 to +75 C * Storage temperature Tstg -55 to +150 C * Allowable power dissipation (Ta 25C) PD 600 mW Operating Conditions * Supply voltage VCC1 - GND1 2.7 to 3.6 VCC2 - GND2 11.0 to 14.0 VDD - VSS 2.7 to 3.6
V V V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E00Y05-PS
CXA3572R
Block Diagram
PSIG DC DET
OSD R
OSD B
B/B-Y
R/R-Y
SIG.C
PSIG OUT
OSD G
VCC1
G/Y
VCC2
NC
+3V MODE
+12V
24 23 22
PICTURE Gain
21 PICTURE f0
20
19
18
17
16
15
14
13
ATT
PICTURE
PSIGBRIGHT DL DL MATRIX
PSIGBRIGHT PSIG PowerSW
SYNC IN 25
ATT ATT DA
HUE COLOR
DA OUT 26 REF 27
DA REF
HUE COLOR
R, G, B SUBCONTRAST
SUBCONT R
SUBCONT B
12 G OUT
FILTER 28
LPF TRAP
LPF SW LPF
CONTRAST
USERBRIGHT USERBRIGHT
GAMMA1 GAMMA2
1 2
SUBBRIGHT
RBRIGHT BBRIGHT
OSD
11 G DC DET 10 R OUT
TRAP
CONTRAST
SYNC SEL SYNC SEP S/H BLIM
9 8
R DC DET B OUT
RPD 29
PHASE COMPARATOR
CLOCK GENERATOR
VCO ADJ Fine VCO ADJ Coarse
BLIM Analog block 3V FRP COM
XSTBY1 HD_ CSYNC XCLP FRP BLK SH1 SH2 SH3 SH4
7
B DC DET
GND1 30
SERIAL I/F
SEN 31 SCK 32
COM Analog block 12V
6 5
COM GND2
DAC
SDAT 33
IR
RP
CK
XSTBY2 Digital block 3V
4
TEST VST VCK EN
SERIAL I/F VD 34 XCLR 35 POF 36 PLL COUNTER
H. FILTER
3 2 1
TIMING GENERATOR
+3V 37 38
VDD HDO
39
VDO
40
RGT
0V 41
VSS
42
HCK1
43
HCK2
44
HST
+3V 45
VDD
46
WIDE
47
DWN
0V 48
VSS
-2-
CXA3572R
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 EN VCK VST TEST GND2 COM B DC DET B OUT R DC DET R OUT G DC DET G OUT VCC2 PSIG OUT PSIG DC DET SIG.C NC OSD B OSD R OSD G VCC1 G/Y R/R-Y B/B-Y SYNC IN DA OUT REF FILTER RPD GND1 SEN SCK SDAT VD XCLR POF Symbol I/O O O O -- -- O O O O O O O -- O O I -- I I I -- I I I I O O O O -- I I I I I O OSD B input OSD R input OSD G input Analog 3.0V power supply G/Y signal input R/R-Y signal input B/B-Y signal input Sync separation circuit input/sync signal input DAC output Level shifter circuit REF voltage output for LCD panel Internal filter circuit f0 adjusting resistor connection Phase comparator output Analog 3.0V GND Serial load input Serial clock input Serial data input Vertical sync signal input Power-on reset capacitor connection (timing output block) LCD panel power supply on/off (Leave this pin open when not using this function.) -3- L EN pulse output V clock pulse output V start pulse output Test (Leave this pin open.) Analog 12.0V GND Common pad voltage output for LCD panel B signal DC voltage feedback circuit capacitor connection B signal output R signal DC voltage feedback circuit capacitor connection R signal output G signal DC voltage feedback circuit capacitor connection G signal output Analog 12.0V power supply PSIG output PSIG signal DC voltage feedback circuit capacitor connection R, G, B and PSIG output DC voltage adjustment Description Input pin for open status
CXA3572R
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48
Symbol VDD HDO VDO RGT VSS HCK1 HCK2 HST VDD WIDE DWN VSS
I/O -- O O O -- O O O -- O O -- Digital 3.0V power supply HDO pulse output VDO pulse output
Description
Input pin for open status
Right/left inversion switching signal output Digital 3.0V GND H clock pulse 1 output H clock pulse 2 output H start pulse output Digital 3.0V power supply WIDE pulse output Up/down inversion switching signal output Digital 3.0V GND
-4-
CXA3572R
Analog Block Pin Description Pin No. 5 Symbol GND2 Pin voltage --
Vcc2
Equivalent circuit
Description Analog 12.0V GND.
125k
6
COM
--
6 5k 100k GND2
COMMON voltage output. The output voltage is controlled by serial communication.
Vcc2
7 9 11 15
B DC DET R DC DET G DC DET PSIG DC DET
7
4K 10k
5k
3.0V
9 11 15 GND2
Smoothing capacitor connection for the feedback circuit of R, G, B and PSIG output signal DC level control. Connect a low-leakage capacitor.
Vcc2
8 10 12 14
B OUT R OUT G OUT PSIG OUT
8
10 10 100k
500 5k
--
10 12 14 GND2
R, G, B and PSIG signal outputs. The DC level is controlled to match the SIG.C pin voltage. Low output in power saving mode.
13
VCC2
12.0V
Vcc2 200k
Analog 12.0V power supply.
16
SIG.C
VCC/2
16 200k GND2 10p
R, G, B and PSIG output DC voltage setting. Connect a 0.01F capacitor between this pin and GND1. When using a SIG.C of other than Vcc2/2, input the SIG.C voltage from an external source.
17
NC
--
No connection.
-5-
CXA3572R
Pin No.
Symbol
Pin voltage
Vcc1
Equivalent circuit
Description OSD pulse inputs. When one of these input pins exceeds the Vth1 level, all of the outputs go to black limiter level; when an input pin exceeds the Vth2 level, only the corresponding output goes to white limiter level. Connect these pins to GND when not used. Analog 3.0V power supply.
18 19 20
OSD B OSD R OSD G
Vth1 = VCC1 x 1/3 Vth2 = VCC1 x 2/3
18 19 20 GND1
20k
21
VCC1
3.0V G/Y: 1.8V
Vcc1
22 23 24
G/Y R/R-Y B/B-Y
R/R-Y, B/B-Y, RGB: 1.8V Y/color difference: 2.0V
22 23 24
1k
GND1
In Y/color difference input mode, input the Y signal to Pin 22, the R-Y signal to Pin 23 and the B-Y signal to Pin 24. In RGB input mode, input the G signal to Pin 22, the R signal to Pin 23 and the B signal to Pin 24. Pedestal clamp these pins with external coupling capacitors.
Vcc1
10k
25
SYNC IN
0.9V
1k 25
Sync separation circuit input, or composite sync/horizontal sync signal input. During input to the sync separation circuit, input via a capacitor.
GND1
Vcc1
80k
26
DA OUT
--
26 15p GND1
DA output. Outputs the serial data converted to DC voltage. The current driving capacity is 1.0mA (max.).
Vcc1
25k
27
REF
VCC1/2
27 100k GND1
REF output. The current driving capacity (sink) is 1.6mA (max.).
-6-
CXA3572R
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description Connect a resistor between this pin and GND1 to control the internal LPF and trap frequencies. Connect a 43k resistor (tolerance 2%, temperature characteristics 200ppm or less). This pin is easily affected by external noise, so make the connection between the pin and external resistor, and between the GND side of the external resistor and the GND1 pin as close as possible.
Vcc1
28
FILTER
1.2V
28
500
GND1
Vcc1
29
RPD
1.8V
1k 29
100k
Phase comparator output.
GND1
30
GND1
--
Vcc1 31 32 1 20k
Analog 3.0V GND.
31 32 33
SEN SCK SDAT
--
33
Serial clock, serial load and serial data inputs for serial communication.
GND1
Vss
-7-
CXA3572R
Digital Block Pin Description Pin No. 1 2 3 36 38 39 40 42 43 44 46 47 Symbol EN VCK VST POF HDO VDO RGT HCK1 HCK2 HST WIDE DWN Pin voltage Equivalent circuit Description
1 36 40 44 2 38 42 46
--
3 39 43 47
Digital block outputs.
Vss
35 31 32 33
XCLR SEN SCK SDAT
35 32
--
31 33
Digital block system reset, and serial clock, serial load and serial data inputs for serial communication.
Vss
34
34
VD
--
Vss
Vertical sync signal input.
37 45 41 48 4
VDD VSS TEST
-- -- --
Digital 3.0V power supply. Digital 3.0V GND. Test. Leave this pin open.
-8-
CXA3572R
Setting Conditions for Measuring Electrical Characteristics Use the Electrical Characteristics Measurement Circuit on page 21 when measuring electrical characteristics. For measurement, the digital block must be initialized and power saving must be canceled by performing Settings 1, 2 and 3 below. In addition, the serial data must be set to the initial settings shown in the table below. Setting 1. System reset After turning on the power, activate the TG block system reset by setting XCLR (Pin 35) Low. The serial bus is set to the default values.
VDD
XCLR (Pin 35)
TR
TR > 10s
System reset
Setting 2. Horizontal AFC adjustment In the condition without sync input, adjust so that the HDO pulse output frequency is NTSC: 15.734 0.1kHz and PAL: 15.625 0.1kHz. Setting 3. Canceling power saving mode The power-on default is power saving mode, so clear (set all "1") serial data PS0 and SYNC GEN.
-9-
CXA3572R
Serial data initial settings MSB ADDRESS LSB MSB D7 0 0 0 0 0 0 PSIGSW (0) 0 0 0 0 LPFSW (0) 0 0 0 0 D6 D5 D4 DATA D3 D2 D1 LSB D0
A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1
USER-BRIGHT SUB-BRIGHT R SUB-BRIGHT B CONTRAST SUB-CONTRAST R SUB-CONTRAST B -1 -2 PSIG-BRIGHT COM-DC COLOR HUE VCO Fine 0 BLACK-LIMITER TRAP (0) PICTURE-GAIN (00000/LSB) LPF (000/LSB)
(10000000/LSB) (1000000/LSB) (1000000/LSB) (10000000/LSB) (1000000/LSB) (1000000/LSB) (0000000/LSB) (0000000/LSB) (1000000/LSB) (1000000/LSB) (1000000/LSB) (1000000/LSB) (10000000/LSB) (100000/LSB) PICTURE-F0 (000/LSB) DA (000/LSB) INPUT SYNC MODE SEL (0) SEL (1) (0) PS0 (1)
VCO Coarse (000/LSB) TEST2 (1) PONF (1)
TEST1 SLPOF SYNC (0) GEN (1) (0) TEST3 (0, 0)
SLSYP SLEXVD SLDWN SLRGT (1) (0) (0) (1) SYST (0) 0 SLFL (0) SLMBK (0)
SLWD SLNTPL (0) (0)
SLFR SL4096 SLCLP1 SLCLP0 SLVDO SLHDO (0) (0) (0) (0) (0) (0) H POSITION (100000/LSB) HDO POSITION (00000/LSB) V POSITION (01000/LSB)
0 S/H POSITION (000/LSB) 1 0 SB POSITION (100/LSB)
TEST4 (00000000/LSB)
Note: If there is the possibility that data may be set at other than the above-noted addresses, set these data to "0".
- 10 -
CXA3572R
Electrical Characteristics -- DC Characteristics Analog Block (Ta = 25C, VCC1 = VDD = 3.0V, VCC2 = 12.0V, see page 10 for the DAC) Item Current consumption 1 (Y/color difference input) Current consumption 2 (Y/color difference input) Current consumption 1 (RGB input) Current consumption 2 (RGB input) Current consumption 1 (PS0 = 0) Current consumption 2 (PS0 = 0) Current consumption 1 (SYNC GEN = 0) Current consumption 2 (SYNC GEN = 0) B DC DET pin voltage R DC DET pin voltage G DC DET pin voltage PSIG DC DET pin voltage SIG.C pin voltage G/Y pin voltage R/R-Y pin voltage 1 R/R-Y pin voltage 2 B/B-Y pin voltage 1 B/B-Y pin voltage 2 SYNC IN pin voltage REF pin voltage (power saving mode) FILTER pin voltage OSD R, G, B input voltage SIG. C input voltage VSIG.C Symbol I1 I2 IRGB1 IRGB2 IPS01 IPS02 ISG1 ISG2 V7 V9 V11 V15 V16 V22 V23 V23 V24 V24 V25 V27 V28 GND 5.0 During Y/color difference input During RGB input During Y/color difference input During RGB input During no input Measurement conditions Measure the inflow current to Pin 21. Measure the inflow current to Pin 13. Measure the inflow current to Pin 21. Measure the inflow current to Pin 13. Measure the inflow current to Pin 21. Measure the inflow current to Pin 13. Measure the inflow current to Pin 21. Measure the inflow current to Pin 13. Min. 16 1.0 12 1.0 -- -- -- -- Typ. 34 3.4 28 3.4 7 0.3 14 0.3 3.0 3.0 3.0 3.0 6.0 1.8 2.0 1.8 2.0 1.8 1.1 0.2 1.2 VCC1 6.5 V Max. 50 10 42 10 mA 11 1.0 27 1.0 Unit
- 11 -
CXA3572R
Item Y1 Y/Color difference mode Y, R-Y, B-Y signal input level 1
Symbol SYNC (Y on SYNC)2 R-Y B-Y Y1 SYNC (Y on SYNC)2 R-Y B-Y R, G, B1 SYNC (G on SYNC)2 R, G, B1 SYNC (G on SYNC)2
Measurement conditions
Min.
Typ. 0.35
Max. 0.4 0.2
Unit
INPUT SEL = 0 (-6dB Attenuate OFF)
0.15 0.245 0.311
0.7 INPUT SEL = 1 (-6dB Attenuate ON) 0.3 0.490 0.622 INPUT SEL = 0 (-6dB Attenuate OFF) 0.35 0.15 0.5 0.2 0.7 0.3 Vp-p
Y/Color difference mode Y, R-Y, B-Y signal input level 2
RGB mode R, G, B signal input level 1 RGB mode R, G, B signal input level 2
INPUT SEL = 1 (-6dB Attenuate ON)
1 Y signal level (SYNC level is not included.) 2 SYNC level of Y (G) on SYNC signal.
- 12 -
CXA3572R
Control Signal Block (Sync signal, serial-serial signal, XCLR, digital output) (Ta = -15 to +75C, VCC1 = VDD = 2.7 to 3.6V) Item High level input voltage Low level input voltage High level input voltage Low level input voltage High level input current Low level input current High level input current Low level input current High level input current Low level input current High level output voltage Low level output voltage High level output voltage Low level output voltage 1 2 3 4 5 6 Symbol Measurement conditions VIH1 VIL1 VIH2 VIL2 | IIH1 | | IIL1 | | IIH2 | | IIL2 | | IIH3 | | IIL3 | VOH1 VOL1 VOH2 VOL2 VIN = VDD VIN = 0V VIN = VDD VIN = 0V VIN = VDD VIN = 0V IOH = -1.2mA IOL = 4.0mA IOH = -0.6mA IOL = 2.0mA 2.6 0.3 2.6 0.3 V 6 20 Min. VCC1 - 0.7 0 2.0 0 Typ. Max. VCC1 0.7 VDD (VCC1) 0.7 20 20 150 1.0 1.0 1.0 A V 2, 3, 4 1, 2 3 (pull-down) 4 5 Unit Applicable pins 1
SYNC IN (Pin 25) SEN (Pin 31), SCK (Pin 32), SDAT (Pin 33) VD (Pin 34) XCLR (Pin 35) HCK1 (Pin 42), HCK2 (Pin 43), HST (Pin 44) EN (Pin 1), VCK (Pin 2), VST (Pin 3), POF (Pin 36), HDO (Pin 38), VDO (Pin 39), RGT (Pin 40), WIDE (Pin 46), DWN (Pin 47)
- 13 -
CXA3572R
Electrical Characteristics AC Characteristics Unless otherwise specified, Settings 1 and 2, the serial data initial settings, and the following setting conditions are required. Ta = 25C, VCC1 = 3.0V, VCC2 = 12V, GND1 = GND2 = 0V, VSS = 0V, SW8/10/12/14 = OFF, no video input, SG1 input to TP25 Note: Serial data values in the table are HEX notation. Item Maximum gain between input and output Minimum gain between input and output Inverted and non-inverted gain difference Symbol GMAX Serial data setting (HEX) Measurement conditions Min. Typ. Max. Unit
Input SG2 (0.2Vp-p) to TP22 and CONT FFh measure the output amplitude at MODE 00h TP12. CONT 00h Input SG2 (0.2Vp-p) to TP22 and MODE 00h measure the output amplitude at TP12. Input SG2 (0.2Vp-p) to TP22 and measure the inverted output amplitude Vinv and the non-inverted output amplitude Vninv at TP12. Ginv = 20 log (Vninv/Vinv)
19
22
25
dB
GMIN
-6
-3
0
dB
GINV
CONT 2Fh
--
--
0.4
dB
Gain difference between R, G and B
GRGB
Input SG2 (0.2Vp-p) to TP22 (TP23, TP24), measure the non-inverted MODE 00h output amplitude at TP8, TP10 and CONT 2Fh TP12, and obtain the maximum and minimum difference between these values. Set CONT = 26h, input SG2 (0.2Vp-p) SUB-CONT to TP22, and assume the non-inverted 00h output amplitude at TP8 and TP10 when SUB-CONT R, B = 40h, 00h and 7Fh as V1, V2 and V3, respectively. SUB-CONT Gsc1 = 20 log (V3/V1) 7Fh Gsc2 = 20 log (V2/V1)
--
--
0.6
dB
GSC1 Sub-contrast variable amount GSC2
-4
-2.0
-1.0 dB
1.0
2.0
4.0
Sub-bright variable amount
VSB1 VSB2
SUB-BRT Set U-BRT = 1Ah and measure the -2.0 R, B 00h non-inverted level at TP8 and TP10 relative to the non-inverted black SUB-BRT level at TP12 when SUB-BRT R, B = 0.9 R, B 7Fh 7Fh and 00h. Measure the R, G, B, PSIG and COM output voltages in power saving mode. BLK-LIM 00h BLK-LIM 3Fh Set U-BRT = 00h, measure the non-inverted black limit level at TP12 when BLK-LIM = 00h and 3Fh, and assume the difference from the output DC voltage as VBL1 and VBL2, respectively.
-1.4 1.4
-0.9 V 2.0
R, G, B, PSIG and COM output VPSO voltage in power saving mode VBL1 Black limiter variable amount VBL2
--
--
100
mV
--
2.5
3.0 V
4.5
5.0
--
- 14 -
CXA3572R
Item
Symbol
Serial data setting (HEX)
Measurement conditions Set CONT = FFh, input SG2 (0.2Vp-p) to TP22, measure the non-inverted white limit level, and obtain the difference from the output DC voltage. Measure the non-inverted black level at TP8, TP10 and TP12, and obtain the maximum and minimum difference between these values. Measure the output DC level (average voltage) at TP8, TP10, TP12 and TP14. Measure the output average voltage difference at TP8, TP10 and TP14 relative to the output average voltage at TP12.
Min.
Typ.
Max. Unit
White limiter variable amount
VWL
0.3
0.6
1.0
V
Black level difference between VB R, G and B RGB and PSIG output DC voltage Vc
--
--
300
mV
5.8
6.0
6.2
V
DC voltage difference between Vc RGB and PSIG VPB1 VPB2 UB1 USER-BRT variable amount UB2
--
--
300
mV
PSIG-BRT variable amount
PSIG-BRT Assume the PSIG output amplitude 00h when PSIG-BRT = 00h and 7Fh as PSIG-BRT VPB1 and VPB2, respectively. 7Fh U-BRT 00h U-BRT FFh SLWD 1 Measure the non-inverted black level at TP12 when U-BRT = 00h and FFh and assume the difference from the average voltage as UB1 and UB2, respectively. Set BLK-LIM = 00h and measure the difference between the inverted and non-inverted black level at TP12 and TP14. Set U-BRT = 80h, CONT = 80h, COLOR = 40h, input SG4 (56mVp-p) to TP23, input SG4 (100mVp-p) to TP24, and assume the amplitude at TP8 when HUE = 80h, 00h and 3Fh as VB1, VB2 and VB3. Similarly, assume the amplitude at TP10 as VR1, VR2 and VR3. HUR1 = 20 log (VR2/VR1) HUR2 = 20 log (VR2/VR1) HUB1 = 20 log (VB2/VB1) HUB2 = 20 log (VB2/VB1) Set CONT = 80h, input SG3 to TP22, and measure the TP12 amplitude at f0 relative to the TP12 amplitude at 100kHz when PIC-G = 00h and 1Fh, respectively. Input SG4 (160mVp-p) to TP23 and TP24, and assume the output amplitude at TP8 and TP10 when COLOR = 00h, 40h and 50h as V1, V2 and V3, respectively. GC1 = 20 log (V1/V2) GC2 = 20 log (V3/V2) - 15 -
8.5 1.0 4.5 1.4
10.0 2.0 4.8 2.0
-- Vp-p -- -- V 2.5
Level difference between PSIG-BLK VBB and BLK-LIM HUR1 HUE variable amount R HUR2 HUB1 HUE variable amount B HUB2 GP1 GP2
--
--
300
mV
HUE 00h
1.5
3
--
HUE 3Fh HUE 00h
--
-5
-2 dB
--
-5
-2
HUE 3Fh PIC-G 00h PIC-G 1Fh COLOR 00h COLOR 50h
1.5 -2.5 9
3 0 12
-- 2.5 dB --
Picture variable amount
GC1 Color variable amount GC2
--
--
-20 dB
0.5
--
--
CXA3572R
Item
Symbol B-Y/ R-Y
Serial data setting (HEX)
Measurement conditions
Min.
Typ.
Max. Unit
Matrix amplitude ratio
G-Y/ R-Y G-Y/ B-Y fc1
Assume the TP10 output when SG4 (0.1Vp-p) is input to TP23 as RR, the TP8 amplitude when SG4 (0.1Vp-p) is input to TP24 as BB, the TP10 amplitude when SG5 CONT 80h (0.1Vp-p) is input to TP23 as RG, COLOR 40h and the TP8 amplitude when SG5 (0.1Vp-p) is input to TP24 as BG. B-Y/R-Y = RR/BB G-Y/R-Y = RG/RR G-Y/B-Y = BG/BB LPF 01h Input SG3 to TP22 and measure the MODE 00h frequency which results in -3dB LPF 07h relative to the TP12 amplitude at MODE 00h 100kHz when LPF = 01h and 07h. Set U-BRT = 30h, CONT = DFh, input SG7 (13.5MHz) to TP22, TP23 MODE 00h and TP24, and measure the amount TRAP 1 by which each output is attenuated relative to SG7 (100kHz). Set SW8, SW10 and SW12 = ON, input SG3 to TP22, TP23 and TP24, MODE 00h and measure the frequency which results in -3dB relative to the TP8, TP10 and TP12 amplitude at 100kHz. Measure the REF pin output voltage at the output current 1.5mA sink. DA 00h DA 07h Output current Measure the DA 1.0mA output voltage when DA = 00h and 07h. Output current -1.0mA
0.85
1.00
1.15
0.41
0.51
0.61
0.15 -- --
0.19 1.5 5.2
0.23 -- MHz --
LPF characteristics fc2
Trap characteristics fo
--
-27
-18
dB
Frequency response
fRGB
5.5
--
--
MHz
REF output voltage VREF DA adjustment range VDA1 VDA2
1.3 -- 2.6
1.5 -- --
1.7 0.3
V
V --
1 gain 2
Input SG2 (0.35mVp-p) to TP22 and measure the amplitude at TP8, TP10 and TP12. Assume the output amplitude when CONT 41h GAMMA1 = 7Fh as V1, when GAMMA1 = 3Fh as V2, and when GAMMA1 = GAMMA2 = 3Fh as V3. 1 = 20 log (V1/V2) 2 = 20 log (V3/V2) Input SG2 (0.35mVp-p) to TP22 and read the gain transition points of the non-inverted output at TP12 when CONT 41h 1 = 00h and 1 = 7Fh from the IRE level of the input signal. 1 = 00h: V 1MN 1 = 7Fh: V 1MX
12
14
16 dB
12
14
16
V 1MN 1 adjustment variable range V 1MX
--
--
0 IRE
100
--
--
- 16 -
CXA3572R
Item
Symbol
Serial data setting (HEX)
Measurement conditions
Min.
Typ.
Max. Unit
V 2MN 2 adjustment variable range V 2MX
Input SG2 (0.35mVp-p) to TP22 and read the gain transition points of the non-inverted output at TP12 when CONT 41h 2 = 00h and 2 = 7Fh from the IRE level of the input signal. 2 = 00h: V 2MN 2 = 7Fh: V 2MX Measure the COM output DC voltage when COM-DC = 00h and 7Fh, and measure the difference from the COM output DC voltage when COM-DC = 40h. Input SG4 to TP18, TP19 and TP20, gradually raise the high level from 0V, and assume the high level voltage at which the output level goes to BLK-LIM level as Vth1OSD, and the high level voltage at which the output goes to WHITE-LIM level as Vth2OSD. SEN setup time, activated by the rising edge of SCK. (See Fig. 3.) SDAT setup time, activated by the rising edge of SCK. (See Fig. 3.) SEN hold time, activated by the rising edge of SCK. (See Fig. 3.) SDAT hold time, activated by the rising edge of SCK. (See Fig. 3.) SCK pulse width. (See Fig. 3.) SCK pulse width. (See Fig. 3.) SEN pulse width. (See Fig. 3.) Measure the transition time of each output. 90pF load: HST output pin 120pF load: HCK1 and HCK2 output pins (See Fig. 1.) Measure the transition time of each output. 50pF load: DWN, WIDE, VCK, VST, TEST, EN, VDO, HDO, POF and RGT output pins (See Fig. 1.) Measure HCK1/HCK2. 120pF load (See Fig. 2.) Measure the HCK1/HCK2 duty. 120pF load - 17 -
100
--
-- IRE
--
--
50
COMMON control range
COMMIN COM-DC 00h COMMX Vth1 OSD COM-DC 7Fh
-1.3 0.8
-1.0 1.0
-0.8 V 1.3
0.8
1.0
1.2 V
OSD threshold value Vth2 OSD ts0 Data setup time ts1 th0 Data hold time th1 tw1L Minimum pulse width tw1H tw2 tTHL
1.8
2.0
2.2
150 150 150 150 210 210 1 --
-- -- -- -- -- -- -- --
-- ns -- -- ns -- -- -- -- 30 ns ns ns s
tTLH Output transition time
--
--
30
tTHL
--
--
40 ns
tTLH
--
--
40
Cross-point time difference HCK duty
T
--
--
--
ns %
DTYHC
48
50
52
CXA3572R
Electrical Characteristic Measurement Method Diagrams
T
90%
50%
10%
tTLH
tTHL
T
Fig. 1. Output transition time measurement conditions
Fig. 2. Cross-point time difference measurement conditions
SDAT
D15 D14 D13 D12 D11 D10 ts1 th1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
SCK
50%
tw1H SEN ts0
tw1L 50%
th0
tw2
Fig. 3. Serial transfer block measurement conditions
- 18 -
CXA3572R
SG No.
Waveform
Horizontal sync signal (CSYNC)
SG1
4.7s 1H
3.0Vp-p
Amplitude variable
SG2
1H Horizontal sync signal
Sine wave video signal; frequency and amplitude variable
0.1Vp-p
SG3
0.1Vp-p 1H
25s
10s
High level variable
SG4
0V
Horizontal sync signal
3V 10s
SG5
Low level variable 25s Horizontal sync signal
- 19 -
CXA3572R
SG No.
Waveform
Horizontal sync signal (CSYNC)
SG6
4.7s 1H
50mVp-p
Sine wave video signal
0.1Vp-p
SG7
1H
SG8
Horizontal sync signal (CSYNC)
4.7ns 1H
0.15Vp-p
- 20 -
CXA3572R
Electrical Characteristics Measurement Circuit
TP29 6800p 10k 3.3
+3V TP36 A 0.01 100k 47 36
POF
TP33 TP32 TP31 0.1 35
XCLR
TP27 TP26 TP25 43k 1 28
FILTER
34
VD
33
SDAT
32
SCK
31
SEN
30
GND1
29
RPD
27
REF
26
DA OUT
25
SYNC IN
0.01 24 0.01 TP23 0.01 TP22 +3V A TP24
37 VDD TP38 TP39 TP40 38 HDO 39 VDO 40 RGT 41 Vss1 TP42 TP43 TP44 42 HCK1 43 HCK2 44 HST 45 VDD TP46 TP47 46 WIDE
B/B-Y R/R-Y 23 G/Y 22 Vcc1 21
OSD G 20 OSD R 19 OSD B 18 NC 17 SIG.C 16 0.1 PSIG DC DET 15
R DC DET G DC DET B DC DET
0.01 TP20 TP19 TP18
47
TP16 0.01 10 SW14 TP14 60n +12V A
47 DWN
B OUT GND2 TEST COM
PSIG OUT 14
G OUT
R OUT
48 Vss2
VCK VST EN
13 VCC2
1
2
3
4
5
6
7
8 10
9
10 10
0.1
11
12 10
0.1
0.1
0.01 TP1 TP2 TP3 TP6
SW10 SW12 SW8
47
350p
350p
TP8
TP10
350p
TP12
Resistance value tolerance: 2%, temperature coefficient: 200ppm/C or less Locate this resistor as close to the IC pin as possible to reduce the effects of external signals.
- 21 -
CXA3572R
Description of Operation 1) RGB and Y/color difference signal processing block Signal processing is comprised of picture, HUE, matrix, LPF/trap, contrast, OSD, sample-and-hold, correction, bright, sub-bright, sub-contrast and output circuits. * Input signal mode switching The input mode (RGB input, Y/color difference input) can be switched by the serial communication settings. (During internal sync separation signal input) During RGB input: The G signal is input to Pins 22 and 25, the B signal to Pin 24, and the R signal to Pin 23. During Y/color difference input: The Y signal is input to Pins 22 and 25, the B-Y signal to Pin 24, and the R-Y signal to Pin 23. (During external sync signal input) During RGB input: The G signal is input to Pin 22, the B signal to Pin 24, the R signal to Pin 23, CSYNC/HD to Pin 25, and VD to Pin 34. During Y/color difference input: The Y signal is input to Pin 22, the B-Y signal to Pin 24, the R-Y signal to Pin 23, CSYNC/HD to Pin 25, and VD to Pin 34. * NTSC/PAL switching The input system (NTSC/PAL) can be switched by the serial communication settings. * Picture circuit This performs aperture correction for the Y signal. The center frequency to be corrected and the correction amount are controlled by serial communication. * HUE circuit This is the hue adjustment circuit for the color difference signal. It is controlled by serial communication. * Matrix circuit This circuit converts Y, R-Y and B-Y signals into RGB signals. * LPF circuit This is the band limitation filter for the RGB signal. It is used to eliminate the noise component generated at the front end of this IC. The cut-off frequency can be controlled by serial communication. In addition, when not using the LPF, it can be turned off by serial communication. * Trap circuit This is used to eliminate the DSP clock and RGB decoder carrier leak generated at the front end of this IC. In addition, when not using the trap, it can be turned off by serial communication. * Contrast adjustment circuit This adjusts the amplitude to set the input RGB signal to the appropriate output level. * OSD This inputs the OSD pulses. There are two input threshold values: Vth1 (Vcc1 x 1/3) and Vth2 (Vcc1 x 2/3). When an input exceeds Vth1, the corresponding output falls to the level specified by BLACK-LIMITER. When an input exceeds Vth2, the corresponding output rises to the level specified by WHITE-LIMITER. Also, when one of the RGB inputs exceeds Vth1, any signal outputs not exceeding Vth1 also fall to the level specified by BLACK-LIMITER. - 22 -
CXA3572R
* Sample-and-hold circuit This circuit performs time axis correction for the RGB output signals in order to support the RGB simultaneous sampling systems of LCD panels.
HCK1
R
S/H1
S/H4
R
A
G
S/H2
S/H4
G
A'
B
S/H3
S/H4
B
B
SH1
SH2
SH3
SH4
B'
RGT = H (Normal) SHS1 SH1 SH2 SH3 SH4 B A C SHS2 A' C' B' SHS3 A C B SHS4 C' B' A' SHS5 C B A SHS6 B' A' C'
C
C'
Through Through Through Through Through Through SH1: R signal SH pulse SH2: G signal SH pulse SH3: B signal SH pulse SH4: RGB signal SH pulse SHS1, 2, 3, 4, 5, 6: Serial data settings
RGT = L (right/left inversion) SHS1 SH1 SH2 SH3 SH4 B A C SHS2 A' C' B' SHS3 A C B SHS4 C' B' A' SHS5 C B A SHS6 B' A' C'
Through Through Through Through Through Through
The sample-and-hold circuit performs sample and hold by receiving the SH1 to SH4 pulses from the TG block. Since LCD panels perform color coding using an RGB delta arrangement, each horizontal line must be compensated by 1.5 dots. This relationship is reversed during right/left inversion. This compensation and other timing is also generated by the digital block. The sample-and-hold timing changes according to the phase relationship with the HCK pulse, so the timing should be set to the SHS1 to SHS6 position in accordance with the actual board. * correction In order to support the characteristics of LCD panels, the I/O characteristics are as shown in Fig. 1. The 1 gain transition point A voltage changes as shown in Fig. 2 by adjusting the serial bus register 1, and the 2 gain transition point B voltage changes as shown in Fig. 3 by adjusting 2.
Output Output A' A B A B B' A B B' Output
Input
Input
Input
Fig. 1
Fig. 2 - 23 -
Fig. 3
CXA3572R
* Bright circuit This is used to adjust the black-black amplitude of polarity-inverted RGB output signals. It is not interlinked with the transition points. * White balance adjustment circuit This is used to adjust the white balance. The black level is adjusted by SUB-BRIGHT, and the black-white amplitude is adjusted by SUB-CONTRAST. * Output circuit RGB output (Pins 8, 10, and 12) signals are inverted each horizontal line by the FRP pulse (internal pulse) supplied from the TG block as shown in the figure below. Feedback is applied so that the center voltage (SIG.C) of the output signal matches the reference voltage (Vcc2 + GND2)/2 (or the voltage input to SIG.C (Pin 16)). In addition, the white level output is clipped at the limiter operation point that is set by the serial communication WHITE-LIMITER, and the black level output is clipped at the limiter operation point that is set by the serial communication BLACK-LIMITER. The output PSIG signal level is normally adjusted by PSIG-BRIGHT, but during black frame display the level is specified by the BLACK-LIMITER level at some timings. In addition, the RGB output also simultaneously goes to BLACK-LIMITER level output.
RGB IN
1H inverted signal (internal) Black frame display signal (internal) BLACK-LIMITER Set by BLACK-LIMITER
PSIG OUT
SIG.C
Set by PSIG-BRIGHT BLACK-LIMITER BLACK-LIMITER
RGB OUT
WHITE-LIMITER SIG.C WHITE-LIMITER
BLACK-LIMITER Set by BLACK-LIMITER
- 24 -
CXA3572R
2) Common voltage generation circuit block The common voltage circuit generates and supplies the common pad voltage to the LCD panel. The voltage is offset by serial communication using the SIG.C voltage as the reference and then output. 3) DA OUT output circuit The DA OUT output circuit outputs DC 3.0V at equal divisions. 4) REF output circuit The REF output circuit generates and supplies the panel level shifter circuit reference voltage to the LCD panel. 5) Sync system * Internal sync separation circuit Sync separation is performed from the signal input from SYNC IN (Pin 25). An external sync signal can also be input from the same pin (SYNC IN) according to the serial communication setting. Serial communication setting SYNC SEL = 0: Internal sync separation. SYNC SEL = 1: External sync signal input. (The internal sync separation circuit is set to power saving mode.) Input pin (Pin 25) processing During internal sync separation: Input through an external capacitor (0.1F) During external sync signal input: Directly coupled, input level 3Vp-p positive or negative polarity * PLL and AFC circuits (VCO setting method) A PLL circuit can be comprised by connecting a PLL circuit phase comparator and frequency division counter and a VCO circuit and external LPF circuit. The PLL error detection signal is generated using the phase comparison output of the entire bottom of the horizontal sync signal and the internal frequency division counter as the RPD output. RPD output is converted to DC error voltage with the lag-lead filter, and then it controls the internal VCO circuit to stabilize the oscillation frequency. The internal clock oscillation frequency is set as follows by adjusting VCO-Coarse/Fine. Adjust the VCO-Coarse/Fine settings so that the HDO pulse output frequency in the condition without sync input is NTSC: 15.734 0.1kHz and PAL: 15.625 0.1kHz.
5MHz Clock oscillation frequency Min: 25MHz Max: 30MHz
VCO-Coarse setting (7 steps) VCO-Coarse: f0 coarse setting (7 steps) from 5 to 25MHz VCO-Fine: Variable by approximately 4MHz using the f0 coarse setting made by VCO-Coarse as the reference
VCO-Fine setting range (255 steps)
6) Power saving circuit (PS circuit) A power saving system can be realized together with the LCD panel by independently controlling (serial communication) the operation of each output block. This system is also effective for improving picture quality during power-on/off. The serial data PS0 and SYNC GEN must be set in order to use this IC. For details of the setting methods, see the "Description of Serial Control Operation" and "Power supply and power saving sequence" items. - 25 -
CXA3572R
7) Power supply and power saving sequence Power-on for the CXA3572R and the LCD panel should be performed in the following order.
Power-on LCD VDD (LCD panel 12V) D1 VCC2 (analog 12V block) B1 VCC1 (analog 3V block) A1 VDD (digital 3V block) A2 C1 C2 B2 D2 Power-off
1 Power saving canceled E1
Power saving set E2
Power saving setting (serial control)
Power saving PS0 = 0, SLSG = 0
Normal operation PS0 1, SLSG 1 12 fields Normal video display
Power saving PS0 0, SLSG 0 4 fields
Display setting period (no video display)
Picture cancel period (no video display)
DA OUT (Pin 26) operation When power saving is set to on or off, video display is automatically turned on or off at the above timings.
Power-on min. A1 B1 C1 D1 E1 0 0 0 1002 0 max. -- -- -- -- 100 ms
Power-off min. A2 B2 C2 D2 E2 0 0 0 3 150 max. -- -- -- -- 300 ms
1 After the digital 3V VDD has completely risen and XCLR (Pin 35) is completely high level. 2 After the 3V VDD/VCC1 has completely risen.
3 After the panel 12V VDD has completely fallen.
* POF (Pin 36) is output as the panel VDD control signal. The POF output can be switched by the serial communication setting, and the POF setting can be made regardless of the power saving setting. SLPOF 0 1 POF (Pin 36) output Low level High Level (VDD)
VDD VCC1
3V power supply VCC2 POF VDD Power supply
CXA3572R
ACX306
Panel power supply configuration using POF output - 26 -
CXA3572R
8) TG block * H-Position This adjusts the horizontal display position. Set this function so that the picture center matches the center of the LCD panel. * V-Position This adjusts the vertical display position. Set this function so that the picture center matches the center of the LCD panel. * Right/left (RGT) and/or up/down (DWN) inversion The video display direction can be switched. The horizontal direction can be switched between right scan and left scan, and the vertical direction between down scan and up scan. Set the display direction in accordance with the LCD panel mounting position. * Overscan display mode (SLWD) Displaying black in the up/down 6 lines and right/left 18 (19) dots of the display area generates an overscan area (black frame) in the display area. Fine adjustment of the black frame display position is performed by SB-Position.
490 dots 453 dots Black display 6 lines
240 lines
Display area
Display area
228 lines
6 lines Normal display Black frame display
* AC driving of LCD panels during no signal The output signal runs freely so that the LCD panel is AC driven even when there is no sync signal from the SYNC IN (Pin 25) and VD (Pin 34) pins.
- 27 -
CXA3572R
Description of Serial Control Operation 1) System reset After turning on the power, activate the TG block system reset by setting XCLR (Pin 35) Low. (See Fig. ) The serial bus is set to the default values.
VDD
XCLR (Pin 35)
TR
TR > 10s
System reset 2) Control method Control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of SCK. This loading operation starts from the falling edge of SEN and is completed at the next rising edge. Digital block control data is established by the vertical sync signal, so if data is transferred multiple times for the same item, the data immediately before the vertical sync signal is valid. Analog (electronic attenuator) block control data becomes valid each time the SEN signal is input. In addition, if 16 bits or more of SCK are not input while SEN is low, the transferred data is not loaded to the inside of the IC and is ignored. If 16 bits or more of SCK are input, the 16 bits of data before the rising edge of the SEN pulse are valid data.
SDAT SCK SEN
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
A: ADDRESS
D: DATA
Serial transfer timing
- 28 -
CXA3572R
2) Serial data map The serial data map is as follows. Values inside parentheses are the default values. MSB ADDRESS LSB MSB D7 (0) (0) (0) (0) (0) (0) PSIGSW (0) (0) (0) (0) (0) LPFSW (0) (0) (0) (0) (0) (0) D6 D5 D4 DATA D3 D2 D1 LSB D0
A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1
USER-BRIGHT SUB-BRIGHT R SUB-BRIGHT B CONTRAST SUB-CONTRAST R SUB-CONTRAST B -1 -2 PSIG-BRIGHT COM-DC COLOR HUE VCO Fine BLACK-LIMITER TRAP (0) PICTURE-GAIN (00000/LSB) LPF (000/LSB)
(10000000/LSB) (1000000/LSB) (1000000/LSB) (10000000/LSB) (1000000/LSB) (1000000/LSB) (0000000/LSB) (0000000/LSB) (1000000/LSB) (1000000/LSB) (1000000/LSB) (1000000/LSB) (10000000/LSB) (100000/LSB) PICTURE-F0 (000/LSB) DA (000/LSB) INPUT SYNC MODE SEL (0) SEL (0) (0) PS0 (0)
VCO Coarse (000/LSB) TEST2 (1) PONF (0)
TEST1 SLPOF SYNC (0) GEN (0) (0) TEST3 (00)
SLSYP SLEXVD SLDWN SLRGT (0) (0) (0) (0) SYST (0) (0) SLFL (0) SLMBK (0)
SLWD SLNTPL (0) (0)
SLFR SL4096 SLCLP1 SLCLP0 SLVDO SLHDO (0) (0) (0) (0) (0) (0) H POSITION (100000/LSB) HDO POSITION (00000/LSB) V POSITION (01000/LSB)
0 S/H POSITION (000/LSB) 1 0 SB POSITION (100/LSB)
TEST4 (00000000/LSB)
Note: If there is the possibility that data may be set at other than the above-noted addresses, set these data to "0".
- 29 -
CXA3572R
3) Description of control data * USER-BRIGHT This adjusts the brightness of the RGB output signals. Adjustment from LSB MSB decreases the amplitude (black - black). * SUB-BRIGHT R/B This adjusts the brightness of the R and B output signals using the G output signal as the reference. Adjustment from LSB MSB decreases the amplitude (black - black). * CONTRAST This adjusts the contrast of the RGB output signals. Adjustment from LSB MSB increases the amplitude (black - white). * SUB-CONTRAST R/B This adjusts the contrast of the R and B output signals using the G output signal as the reference. Adjustment from LSB MSB increases the amplitude (black - white). * -1 This sets the black side point level of the RGB output signals. Adjustment from MSB LSB lowers the point. When not adjusting -1, set -1: 0000000 (LSB). Set the -1 point to the black side (lower side) of the -2 point. * -2 This sets the white side point level of the RGB output signals. Adjustment from LSB MSB lowers the point. When not adjusting -2, set -2: 0000000 (LSB). Set the -2 point to the white side (upper side) of the -1 point. * PSIG-BRIGHT This adjusts the brightness of the PSIG output signal. Adjustment from LSB MSB decreases the amplitude (peak to peak). * PSIG-SW This switches the PSIG circuit on and off. D7 0 1 Mode PSIG OFF PSIG ON
* COM-DC This adjusts the COMMON output voltage. Adjustment from LSB MSB increases the output voltage. * COLOR This adjusts the color gain during Y/color difference input. Adjustment from LSB MSB increases the gain. * HUE This adjusts the phase during Y/color difference input. Adjustment from LSB MSB advances the phase. - 30 -
CXA3572R
* VCO-Fine This finely adjusts the VCO oscillation center frequency. Adjustment from LSB MSB increases the frequency. Perform this adjustment after adjusting VCO-Coarse. * VCO-Coarse This roughly adjusts the VCO oscillation center frequency. Adjustment from LSB MSB increases the frequency. Adjust with VCO-Fine set to 10000000 (LSB). * BLACK-LIMITER This adjusts the black side limiter level of the RGB output signals. Adjustment from LSB MSB lowers the limiter level. * PICTURE-GAIN This adjusts the picture gain during Y/color difference input. Adjustment from LSB MSB raises the gain. When not using the picture function, set PICTURE-GAIN: 00000 (LSB). * PICTURE-F0 This sets the picture center frequency (f0) during Y/color difference input. See the AC Characteristics for the output level. D2 0 0 0 0 1 1 1 1 D1 D0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Center frequency (f0) typ. 1.0MHz 1.3MHz 1.6MHz 1.9MHz 2.2MHz 2.5MHz 2.8MHz 3.1MHz
* LPF This switches the frequency response of the low-pass filter. Set the fc/-3dB frequency relative to the amplitude 100kHz reference. See the AC Characteristics for the output level. D6 0 0 0 0 1 1 1 1 D5 D4 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fc (RGB input/no load/typ.) -- 1.5MHz 2.1MHz 2.7MHz 3.5MHz 4.1MHz 4.6MHz 5.2MHz - 31 -
CXA3572R
* LPF-SW This switches the LPF circuit on and off. D7 0 1 Mode LPF off LPF on
* TRAP This switches the trap circuit on and off. D3 0 1 Mode TRAP off TRAP on
* DA This adjusts the DA output voltage. Adjustment from LSB MSB raises the output voltage level. * INPUT-SEL Set this according to the input signal level. D2 0 1 Normal input Internally attenuated by -6dB Mode Input signal level 0.35Vp-p or less, 0.5Vp-p or less with sync 0.35Vp-p or more, 0.5Vp-p or more with sync
* SYNC SEL This switches between internal sync separation and external sync signal input. D1 0 1 Mode Internal sync separation External sync signal input (internal sync separation circuit power saving) Input connection method Input via a coupling capacitor Input level 3Vp-p positive or negative polarity
* MODE This switches the input signal. D0 0 1 Input signal RGB input Y/color difference input
* PS0 (Default: 0) This performs the power saving setting. Be sure to use this setting as described in "Power supply and power saving sequence". The power-on default for this IC is power saving mode, so the settings should be canceled by serial communication after power-on. The LCD panel power supply must be turned off in power saving mode. PS0 0 1 Power saving Normal operation - 32 - Mode
CXA3572R
* SYNC GEN (Default: 0) This sets the sync generator mode. In sync generator mode, only the HDO and VDO pulses are output normally, and all other pulses are low. The LCD panel power supply must be turned off in sync generator mode. Normally set to "1". SYNC GEN 0 1 Mode Sync generator mode Normal operation
* SLPOF (Default: 0) This sets the POF (Pin 36) output. The POF output setting can be made regardless of the power saving mode. SLPOF 0 1 Mode POF = Low output POF = High output
* TEST1 (Default: 0) This is the test mode. Set to "0". TEST0 0 1 Mode Normal operation Test mode
* PONF (Default: 0) This switches the time until the picture is displayed after power saving is canceled. PONF 0 1 12 fields 4 fields Mode
* TEST2 (Default: 0) This is the test mode. Set to "1". TEST2 0 1 Test mode Normal operation Mode
* SLNTPL (Default: 0) This switches between NTSC and PAL mode. SLNTPL 0 1 NTSC PAL - 33 - Mode
CXA3572R
* SLWD (Default: 0) This sets the up/down and/or right/left black frame display. SLWD 0 1 Display 100% viewing field display Black frame display (95% display)
* TEST3 (Default: 0, 0) This is the test mode. Set to "0, 0". TEST3 0, 0 0, 1 1, 0 1, 1 Mode Normal operation Test mode
* SLRGT (Default: 0) This switches between normal and right/left inverted display. SLRGT 0 1 Setting Normal display (right scan) Right/left inverted display (left scan)
* SLDWN (Default: 0) This switches between normal and up/down inverted display. SLDWN 0 1 Setting Normal display (down scan) Up/down inverted display (up scan)
* SLEXVD (Default: 0) This sets the external VD input. The external VD signal is input via VD (Pin 34). When using internal vertical sync separation, vertical sync separation is performed using the CSYNC input from SYNC IN (Pin 25). SLEXVD 0 1 Setting Internal vertical sync separation External VSYNC input
* SLSYP (Default: 0) This switches the input sync signal polarity. When performing sync separation with the internal sync separation circuit from YonSYNC or GonSYNC, set this to "0". SLSYP 0 1 HD/CSYNC, VSYNC polarity Positive polarity Negative polarity - 34 -
CXA3572R
* SLHDO (Default: 0) This switches the HDO pulse output polarity. SLHDO 0 1 HDO polarity Positive polarity Negative polarity
* SLVDO (Default: 0) This switches the VDO pulse output polarity. SLVDO 0 1 VDO polarity Positive polarity Negative polarity
* SLCLP0, SLCLP1 (Default: 0, 0) These switch the clamp position. SLCLP1 0 0 1 1
HSYNC
SLCLP0 0 1 0 1
Position A: Back porch position (during internal sync separation) B: Sync position (during internal sync separation) C: Back porch position (during external sync signal input) D: Sync position (during external sync signal input)
00: A 01: B XCLP 10: C 11: D
2.0s 1.3s 2.9s 2.0s 2.0s 1.0s 3.6s 2.0s
* SL4096 (Default: 0) This function inverts the R, G, B and PSIG output signal polarities every 4096 fields. This further inverts the output polarities that are inverted every 1H for 4096 fields. SL4096 0 1 Polarity inversion cycle 1H inversion 1H inversion + 4096-field inversion
* SLFR (Default: 0) This function inverts the R, G, B and PSIG output signal polarities every field. Normally set to 1H inversion. SLFR 0 1 Polarity inversion cycle 1H inversion 1-field inversion - 35 -
CXA3572R
* SLFL (Default: 0) This function is used to stop R, G, B and PSIG output signal polarity inversion. SLFL 0 1 Polarity inversion cycle Polarity inversion Polarity inversion stopped
* SYST (Default: 0) This invalidates the input sync (CSYNC, HD/VD) and forcibly sets the free-running status. SYST 0 1 Mode Normal operation Forced free-running
* H POSITION (Default: 100000/LSB) These set the horizontal display position. The HST pulse position is adjusted using the horizontal sync signal as the reference. Adjustment is possible in 1 bit = 1fH increments.
HSYNC HP: 100000 (LSB) Default HP: 000000 (LSB) HP: 111111 (LSB) 30 steps (fH) 31 steps (fH)
HST
* SLMBK (Default: 0) This sets the decimation cycle in PAL mode. SLMBK 0 1 Decimation cycle 1/6, 1/6 decimation 1/6, 1/8 decimation
* HDO POSITION (Default: 10000/LSB) These set the HDO pulse output position. The HDO pulse output position is adjusted using the horizontal sync signal as the reference. Adjustment is possible in 1 bit = 4fH increments.
HSYNC HP: 00000 (LSB) Default HDO HP: 11111 (LSB)
31 steps (124fH)
- 36 -
CXA3572R
* V POSITION (Default: 01000/LSB) These set the vertical display position. The VST pulse position is adjusted using the input vertical sync signal as the reference. Adjustment is possible in 1 bit = 1H (1 line) increments.
Vertical sync signal VP: 01000 (LSB) Default VP: 00000 (LSB) VP: 11111 (LSB) 8 steps (8H) 23 steps (23H)
VST
* S/H POSITION (Default: 000/LSB) These set the sample-and-hold pulse output phase. D7 D6 D5 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Sample-and-hold position SHS1 SHS2 SHS3 SHS4 SHS5 SHS6 Through (sample-and-hold off) Through (sample-and-hold off)
* SB POSITION (Default: 100/LSB) In overscan display mode, fine adjustment of the right/left overscan area (black frame) position is possible in 1 bit = 1fH increments.
HST SBP: 000 (LSB) (BLK) SBP: 100 (LSB) SBP: 111 (LSB) 4 steps 3 steps (3fH) (4fH) 4 steps 3 steps (4fH) (3fH)
* TEST4 (Default: 00000000/LSB) This is the test mode. Set to 00000000/LSB (8 bits).
- 37 -
CXA3572R
Application Circuit
External HD Input (0 to 3V) To LCD Panel 3.3
External VD Input
Serial Data Input
0.1
43k
6800p
1
0.1 100k 36
POF
35
XCLR
34
VD
33
SDAT
32
SCK
31
SEN
30
GND1
29
RPD
0.01
10k
28
FILTER
27
REF
26
DA OUT
25
SYNC IN
37 VDD
0.1 B/B-Y 24 0.1 R/R-Y 0.1 G/Y 22 Vcc1 21 G/Y 0.1 +3V (Analog) B/B-Y
38 HDO 39 VDO 40 RGT 41 Vss1 42 HCK1 To LCD Panel 43 HCK2 44 HST 45 VDD 46 WIDE 47 DWN
G DC DET R DC DET B DC DET R OUT B OUT GND2 TEST
R/R-Y 23
OSD G 20 OSD R 19 OSD B 18 NC 17 SIG.C 16 0.68 PSIG DC DET 15 Buffer PSIG 14 OUT
G OUT
33
0.01
2
48 Vss2
VCK VST
10 0.1
To LCD Panel
COM
0.1
EN
VCC2
13
1 +3V (Digital)
2
3
4
5
6
7
8
9
10
11
12 +12V (Analog)
0.68
0.68
To LCD Panel 33
10
10
10
0.68
33
33
10
To LCD Panel
1 2
Resistance value tolerance: 2%, temperature coefficient: 200ppm/C or less When using a signal center voltage other than Vcc2/2, input an external signal center voltage.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 38 -
CXA3572R
Notes on Operation (1) This IC contains digital circuits, so the set board pattern must be designed in consideration of undesired radiation, interference to analog circuits, etc. Care should also be taken for the following items when designing the pattern. * The digital and analog IC power supplies should be separated, but the GND and VSS should not be separated and should use a plain GND (VSS) pattern in order to reduce impedance as much as possible. The power supplies should also use a plain pattern. * Use ceramic capacitors for the by-pass capacitors between the power supplies and GND, and connect these capacitors as close to the pins as possible. * The resistor connected to Pin 28 should be connected as close to the pin as possible, and the wiring from the pin to GND should be as short as possible. Also, do not pass other signal lines close to this pin or the connected resistor. (2) The G/Y (Pin 22), R/R-Y (Pin 23), B/B-Y (Pin 24) and SYNC IN (Pin 25) pin input signals are clamped at the inputs using the capacitors connected to each pin, so these signals should be input at sufficiently low impedance. (Input at an impedance of 1k (max.) or less.) The smoothing capacitor of the DC level control feedback circuit in the capacitor block connected to the RGB output pins should have a leak current with a small absolute value and variance. Also, when using the pulse elimination (PAL display) function, the picture quality should be thoroughly evaluated before deciding the capacitance value of the capacitor. A thorough study of whether the capacitor connected to the COM output pin satisfies the LCD panel specifications should be made before deciding the capacitance value. If this IC is used in connection with a circuit other than an LCD, it may cause that circuit to malfunction depending on the order in which power is supplied to the circuits. Thoroughly study the consequences of using this IC with other circuits before deciding on its use. Since this IC utilizes a C-MOS structure, it may latch up due to excessive noise or power surge greater than the maximum rating of the I/O pins, or due to interface with the power supply of another circuit, or due to the order in which power is supplied to circuits. Be sure to take measures against the possibility of latch up. Be sure to observe the power supply and power saving sequence specifications specified for this IC. Do not apply a voltage higher than VDD or lower than VSS to I/O pins. Do not use this IC under operating conditions other than those given.
(3)
(4)
(5)
(6)
(7) (8) (9)
(10) Absolute maximum rating values should not be exceeded even momentarily. Exceeding ratings may damage the device, leading to eventual breakdown. (11) This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should be taken to prevent electrostatic discharge. (12) Always connect the VSS, GND1 and GND2 pins to the lowest potential applied to this IC; do not leave these pins open. The voltages applied to the power supply pins should be as follows. VSS = GND1 = GND2 VDD = VCC1 VCC2. (13) Be sure to connect the damping resistor of 10 to ROUT, GOUT, BOUT, PSIGOUT and COM output. - 39 -
CXA3572R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 0.2 36 37 7.0 0.1 25 24 S
(8.0)
A 48 1 0.5 + 0.08 0.18 - 0.03 + 0.2 1.5 - 0.1 12 13
B
(0.22)
+ 0.05 0.127 - 0.02 0.13 M
0.1 0.1 0.1
0.5 0.2
S
0.18 0.03
0 to 10
0.5 0.2
DETAIL B: PALLADIUM DETAIL A NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 P-LQFP48-7x7-0.5 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.2g
0.127 0.04
- 40 -
Sony Corporation

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